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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners 12-bit, 125ksps low-power adcs with single-ended and differential inputs and multiple input channels isl26310, isl26311, isl26312, isl26313, isl26314, isl26315, isl26319 the isl26310/11/12/13/14/15/19 family of sampling sar-type adcs feature excellent linearity over supply and temperature variations, and offer versions with 1-, 2-, 4- and 8-channel single-ended inputs, and 1-, 2- and 4-channel differential inputs. a proprietary input multiplexer and combination buffer amplifier reduces the input drive requiremen ts, resulting in lower cost and reduced board space. specified measurement accuracy is maintained with input signals up to vdd. members of the isl26310/11/12/13/14/15/19 family of low-power adcs offer pinout intercompatibility, differing only in the analog inputs, to support quic k replication of proven layouts across multiple design platforms. the serial digital interface is spi compatible and is easily interfaced to popular fpgas and microcontrollers. power consumption is limited to 11mw at a sampling rate of 125ksps, and an operating current of just 8a typical between conversions, when configured for auto powerdown mode. the isl26310/11/12/13/14/15/19 feature up to 5kv human body model esd survivability and are available in the popular soic and tssop packages. performance is specified for operation over the full industri al temperature range (-40c to +125c). features ? pin-compatible family allows easy design upgrades ? excellent differential non-linearity (0.7lsb max) ? low thd: -86db (typ) ? simple spi-compatible serial digital interface ? low 2.2ma operating current ? power-down current between conversions 8a (typ) ? +5.25v to +2.7v supply ? excellent esd survivability: 5kv hbm, 350v mm, 2kv cdm applications ? industrial process control ? energy measurement ? multichannel data acquisition systems ? pressure sensors ? flow controllers figure 1. functional block diagram osc adc mux spi por analog inputs differential/ single-ended vref vdd cnv sclk sdo sdi gnd buffer july 3, 2012 fn7549.1
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 2 fn7549.1 july 3, 2012 application block diagram pin-compatible family model resolution (bits) speed (khz) analog input input channels isl26310 12 125 differential 1 isl26311 12 125 single-ended 1 isl26312 12 125 differential 2 isl26313 12 125 single-ended 2 isl26314 12 125 differential 4 isl26315 12 125 single-ended 4 isl26319 12 125 single-ended 8 isl26320 12 250 differential 1 isl26321 12 250 single-ended 1 isl26322 12 250 differential 2 isl26323 12 250 single-ended 2 isl26324 12 250 differential 4 isl26325 12 250 single-ended 4 isl26329 12 250 single-ended 8 power rs-485 -v +v -v +v m u x adc analog signal input modules rtc voltage monitors & watchdog core & i/o power isolated power sw controller gain amplifier active filter c ldos v-ref v-ref differential pressure transducer w/ sqrt extractor pressure/strain gage sensor temperature sensor flow sensor dcp -v +v -v precision amp gain amplifier active filter -v +v -v gain amplifier active filter +v +v mux and adc thermal couple iso-thermal block rtd loop supply 4-20ma vin iout dcp switching regulators system power precision amp precision amp precision amp precision amp precision amp precision amp
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 3 fn7549.1 july 3, 2012 ordering information part number (notes 1, 2, 3) part marking description temp. range (c) package (pb-free) pkg dwg # resolution (bits) speed (khz) input (se/diff) input channels isl26310fbz 26310 fbz 12 125 diff 1 -40 to +125 8 ld soic m8.15 isl26311fbz 26311 fbz 12 125 se 1 -40 to +125 8 ld soic m8.15 ISL26312FVZ 26312 fvz 12 125 diff 2 -40 to +125 16 ld tssop m16.173 isl26313fbz 26313 fbz 12 125 se 2 -40 to +125 8 ld soic m8.15 isl26314fvz 26314 fvz 12 125 diff 4 -40 to +125 16 ld tssop m16.173 isl26315fvz 26315 fvz 12 125 se 4 -40 to +125 16 ld tssop m16.173 isl26319fvz 26319 fvz 12 125 se 8 -40 to +125 16 ld tssop m16.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl26310 , isl26311 , isl26312 , isl26313 , isl26314 , isl26315 , isl26319. for more information on msl please see techbrief tb363 .
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 4 fn7549.1 july 3, 2012 pin configurations isl26310 (8 ld soic) top view isl26311 (8 ld soic) top view isl26313 (8 ld soic) top view isl26312 (16 ld tssop) top view isl26314 (16 ld tssop) top view isl26315 (16 ld tssop) top view isl26319 (16 ld tssop) top view 1 2 3 4 5 7 6 ain+ ain- gnd vdd cnv sdi sclk sdo 8 1 2 3 4 5 7 6 vref ain0 gnd vdd cnv sdi sclk sdo 8 1 2 3 4 5 7 6 ain0 ain1 gnd vdd cnv sdi sclk sdo 8 1 2 3 4 5 6 7 9 10 11 12 13 15 14 ain0+ ain0- gnd vref ain1+ ain1- vdd nc nc nc cnv sdi sclk sdo 16 nc 8 gnd ain0+ ain0- ain1+ ain1- ain3- ain3+ ain2- ain2+ 1 2 3 4 5 6 7 9 10 11 12 13 15 14 gnd vref vdd cnv sdi sclk sdo 16 8 gnd ain0 ain1 ain2 ain3 nc nc nc nc 1 2 3 4 5 6 7 9 10 11 12 13 15 14 gnd vref vdd cnv sdi sclk sdo 16 8 gnd ain0 ain1 ain2 ain3 ain6 ain7 ain4 ain5 1 2 3 4 5 6 7 9 10 11 12 13 15 14 gnd vref vdd cnv sdi sclk sdo 16 8 gnd
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 5 fn7549.1 july 3, 2012 pin descriptions pin name pin number description isl26310 isl26311 isl26312 isl26313 isl26314 isl26315 isl26319 vdd 1 1 1 1 1 1 1 positive supply voltage gnd 2 2 2, 4 2 2, 4 2, 4 2, 4 ground vref - 3 3 - 3 3 3 reference voltage input ain0+ - - 5 - 5 - - differential analog input, positive ain0- - - 6 - 6 - - differential analog input, negative ain1+ - - 7 - 7 - - differential analog input, positive ain1- - - 8 - 8 - - differential analog input, negative ain2+ - - - - 10 - - differential analog input, positive ain2- - - - - 9 - - differential analog input, negative ain3+ - - - - 12 - - differential analog input, positive ain3- - - - - 11 - - differential analog input, negative ain0 - 4 - 3 - 5 5 single-ended analog input ain1 - - - 4 - 7 6 single-ended analog input ain2 - - - - - 10 7 single-ended analog input ain3 - - - - - 12 8 single-ended analog input ain4 - - - - - - 9 single-ended analog input ain5 - - - - - - 10 single-ended analog input ain6 - - - - - - 11 single-ended analog input ain7 - - - - - - 12 single-ended analog input sdi 5 5 13 5 13 13 13 serial interface data input sdo 6 6 14 6 14 14 14 serial interface data output sclk 7 7 15 7 15 15 15 serial interface clock input cnv 8 8 16 8 16 16 16 conversion control input nc - - 9, 10, 11, 12 - - 6, 8, 9, 11 - no connect ain+ 3 - - - - - - differential analog input, positive ain- 4 - - - - - - differential analog input, negative
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 6 fn7549.1 july 3, 2012 absolute maximum rating s thermal information ain+, ain-, vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to v dd +0.3v digital inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to v dd +0.3v vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6v gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to +0.3v esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . . . . .5000v machine model (per jesd22-a115). . . . . . . . . . . . . . . . . . . . . . . . . . 350v charged device model (per jesd22-c101) . . . . . . . . . . . . . . . . . . . . . . 2000v latch-up (tested per jesd-78b; class 2, level a). . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic (notes 4, 5) . . . . . . . . . . . . . . . . . 98 48 16 ld tssop (notes 4, 5) . . . . . . . . . . . . . . 92 29 maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7v to +5.25v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test level or notes min (note 6) typ max (note 6) units analog inputs number of input channels isl26310, isl26311 1 isl26312, isl26313 2 isl26314, isl26315 4 isl26319 8 input voltage range differential inputs (ainx+ - ainx-) is -v ref (min) and +v ref (max) 0v ref v ainx, single-ended inputs 0v ref v common mode input voltage range differential inputs v ref /2 ? 0.2 v ref/2 v ref /2 + 0.2 v average input current 2.5 a c in input capacitance 4pf channel-channel crosstalk f in = 100khz v in = fs, other channels = 0v -86 db voltage reference v refex external reference input voltage range 2 2.5 v dd v i refin average input current 100 120 a c refin effective input capacitance 10 pf dc accuracy resolution (no missing codes) 12 bits dnl differential nonlinearity error -0.7 +0.7 lsb inl integral nonlinearity error -0.7 +0.7 lsb gain error -6 6 lsb gain error matching -2 2 lsb offset error -6 6 lsb offset error matching -2 2 lsb
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 7 fn7549.1 july 3, 2012 psrr power supply rejection ratio 70 db dynamic performance snr signal-to-noise notes: v in = fs-0.1db, f in = 10khz differential inputs 73.4 db single-ended inputs 73.4 db sinad signal-to-noise + distortion notes: v in = fs-0.1db, f in = 10khz differential inputs 73.1 db single-ended inputs 73.1 db thd total harmonic distortion notes: v in = fs-0.1db, f in = 10khz differential inputs -86 db single-ended inputs -86 db sfdr spurious-free dynamic range notes: v in = fs-0.1db f in = 20khz 96 db bw -3db input bandwidth 2.5 mhz t ad sampling aperture delay 12 ns t jit sampling aperture jitter 25 ps power supply requirements v dd supply voltage 2.7 5.25 v i dd supply current 2.2 3 ma pd power consumption normal operation 11 15 mw ipd power-down current auto power-down mode 8 50 a istby standby mode current auto sleep mode 0.4 ma digital inputs v ih 0.7 vdd v v il 0.2 v dd v v oh i oh = -1ma vdd-0.4 v v ol i ol = 1ma 0.2 v dd v i ih , i il input leakage current -100 100 na serial clock frequency 20 mhz timing specifications (note 7) t sclk sclk period (in rac mode) 50 ns t sclk sclk period (in rsc, rdc modes) 50 200 ns t data safe data transfer time after conversion state begins 3.2 s t csb_sclk csb falling low to sclk rising edge 40 ns t sdi_su sdi setup time with respect to positive edge of sclk 10 ns t sdi_h sdi hold time with respect to positive edge of sclk 10 ns t sdo_v sdout valid time with respect to negative edge of sclk 25 ns t sdoz_d sdout to high impedance state after cnv rising edge (or last sclk falling edge) note 8 85 ns t acq acquisition time when fully powered up 800 ns t acq acquisition time in auto sleep mode 2.1 s electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test level or notes min (note 6) typ max (note 6) units
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 8 fn7549.1 july 3, 2012 t acq acquisition time in auto power down mode 150 s t sclkh sclk high time 20 ns t sclkl sclk low time 20 ns t cnv cnv pulse width 100 ns notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. the device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a power cycle to restore normal operation. 8. transition time to high impedance state is dominated by rc loading on the sdout pin. specified value is measured using equiva lent loading shown in figure 2. electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test level or notes min (note 6) typ max (note 6) units figure 2. equivalent load circuit for digital output testing output pin c l 10pf vdd 2k r l
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 9 fn7549.1 july 3, 2012 typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 125khz, f sclk = 20mhz, unless otherwise specified. figure 3. differential nonlinearity (dnl) vs code figure 4. integral nonlinearity (inl) vs code figure 5. dnl distribution vs temperature f igure 6. inl distributi on vs temperature figure 7. gain error vs supply voltag e and temperature figure 8. offset erro r vs supply voltage and temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 code dnl (lsbs) -2000 -1000 0 1000 2000 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 code inl (lsbs) -2000 -1000 0 1000 2000 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 temperature (c) dnl negative dnl positive dnl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 temperature (c) inl negative inl positive inl -40 -20 0 20 40 60 80 100 120 temperature (c) gain error (lsb) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 5.0v 5.25v 2.7v 3.3v -40 -20 0 20 40 60 80 100 120 temperature (c) -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 3.3v 5.0v 5.25v 2.7v offset error (lsb)
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 10 fn7549.1 july 3, 2012 figure 9. aperture delay vs supply voltage figur e 10. supply current vs voltage and temperature figure 11. supply current vs sampling rate (v dd = 5v) figure 12. shutdown curren ts vs voltage and temperature figure 13. snr and sinad vs supply voltage and temper ature figure 14. thd vs supply voltage and temperature typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 125khz, f sclk = 20mhz, unless otherwise specified. (continued) 0 5 10 15 20 25 2.7 3.2 3.7 4.2 4.7 5.2 a p e r t u r e d e l a y ( n s) supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 40 60 80 100 120 s u p p ly c u r r e n t ( m a ) temperature (c) 5.25v 3.3v 5.0v 2.7v 0.0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k sample rate (sps) supply current (ma) auto power down mode auto sleep mode normal mode 0 5 10 15 20 25 30 35 40 45 50 -40 -20 0 20 40 60 80 100 120 temperature (c) shutdown current (a) 5.25v 3.3v 5.0v 2.7v 70 71 72 73 74 75 -40 -20 0 20 40 60 80 100 120 temperature (c) 5.25v 3.3v 5.0v 2.7v snr/sinad (db) -90 -88 -86 -84 -82 -80 -40-20 0 20406080100120 temperature (c) thd (db) 5.25v 3.3v 5.0v 2.7v
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 11 fn7549.1 july 3, 2012 figure 15. snr and sinad vs input freq uency figure 16. thd vs input frequency figure 17. single-tone fft figure 18. shorted input histogram typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 125khz, f sclk = 20mhz, unless otherwise specified. (continued) 55 60 65 70 75 100 1k 10k 100k 1m input frequency (hz) snr/sinad (db) snr sinad -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k 100k 1m input frequency (hz) thd (db) 0 1020304050 6070 frequency (khz) -160 -140 -120 -100 -80 -60 -40 -20 0 amplitude (db) snr: 72.93db sinad: 72.71db thd: -85.84db sfdr: 96.16dbc enob: 11.79 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 -3 -2 -1 0 1 2 3 code 65,536 codes 0 codes 0 codes hits
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 12 fn7549.1 july 3, 2012 circuit description the isl26310/11/12/13/14/15/19 family of 12-bit adcs are low-power successive approximation-type (sar) adcs with 1-, 2-, 4-, or 8-channels and a choice of single-ended or differential inputs. the high-impedance buffered input simplifies interfacing to sensors and external circuitry. the entire isl26310/11/12/13/14/15/19 family follows the same base pinout and differs on ly in the analog input pins, allowing the user to replicate the basic board layout across multiple platforms with a minimum redesign effort. the simple serial digital interface is compatible with popular fpgas and microcontrollers and al lows direct conversion control by the cnv pin. functional description the isl26310/11/12/13/14/15/19 devices are sar (successive approximat ion register) analog-to-digital converters that use capacitor-based charge redistribution as their conversion method. these devices include an on-chip power-on reset (por) circuit to initialize the internal digital logic when power is applied. an on-chip oscillator provides the master clock for the conversion logic. the cnv signal controls when the converter enters into its signal acquisition time (cnv = 0), and when it begins the conversion sequence after the signal has been captured (cnv = 1). the converters include a configuration register that can be accessed via the serial port. the configuration register has various bits to indicate which channel (where applicable) is selected, to activate the auto-power-down feature where the adc is shut down between conversions, or to output the configuration register contents along with the data conversion word whenever a conversion word is read from th e serial port. the serial port supports three different modes of reading the conversion data. these will be discussed later in this data sheet. figures 19 and 20 illustrate simplified representations of the converter analog section for differ ential and single-ended inputs, respectively. during the acquisition phase (cnv = 0) the input signal is presented to the cs samples capacitors. to properly sample the signal, the cnv signal must remain low for the specified time. when cnv is taken high (cnv = 1), the switches that connect the sampling capacitors to the input are opened and the control logic begins the successive approximation sequence to convert the captured signal into a digital word. the conversion sequence timing is determined by the on-chip oscillator. adc transfer function the isl26310, the isl26312, and the isl26314 feature differential inputs with output data coding in two's complement format (see table 1). the size of one lsb in these devices is (2*vref)/4096. figure 21 on page 13 illustrates the ideal transfer function for these devices. the isl26311, isl26313, isl26315, and isl26319 feature single-ended inputs with output coding in binary format (see table 2). the size of one lsb in these devices is vref/4096. figure 22 on page 13 illustrates the ideal transfer function for these devices. figure 19. architectural block diagram, differential input figure 20. architectural block diagram, single-ended ain+ ain ? vref acq cnv acq acq cnv cnv dac dac sar logic buffer vcm cnv acq comparator vref c s c s ain vref acq cnv acq acq cnv cnv dac dac sar logic buffer vcm cnv acq comparator c s c s
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 13 fn7549.1 july 3, 2012 analog inputs some members of the isl263 10/11/12/13/14/15/19 family feature a fully differential input with a nominal full-scale range equal to twice the applied vref voltage. those devices with differential inputs have a nominal full scale range equal to twice the applied vref voltage. each input swings vref volts (peak-to- peak), 180 out of phase from one another for a total differential input of 2*vref (refer to figures 23 and 24). differential signaling offers seve ral benefits over a single-ended input, such as: ? doubling of the full-scale input range (and therefore the dynamic range) ? improved even order harmonic distortion ? better noise immunity due to common mode rejection figure 24 shows the relationship between the reference voltage and the full-scale differential input range for two different values of vref. note that the common -mode input voltage must be maintained within 200mv of vr ef/2 for differential inputs. those devices with singled-ended inputs have a ground- referenced peak-to-peak inpu t voltage span equal to the reference voltage. figure 21. ideal transfer characteristics, differential input figure 22. ideal transf er characteristics, single-ended input 1lsb = 2?vref/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 adc code analog input ain+ ? (ain?) ? vref + ?lsb +vref ? 1?lsb 0v +vref ? 1lsb 1lsb = 2?vref/4096 000...000 000...001 000...010 011...111 100...000 100...001 111...110 111...111 adc code analog input ? vref + ?lsb +vref ? 1?lsb +vref ? 1lsb figure 23. differential input signaling isl2631x/32x v cm v ref pp v ref pp ain+ ain- figure 24. relationship between vref and full-scale range for differential inputs 3.0 5.0 2.0 1.0 4.0 ain+ ain? 2.5vpp vref = 2.5v 3.0 5.0 2.0 1.0 4.0 ain+ ain? vcm 5vpp vref = 5v t v t v allowable vcm range allowable vcm range
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 14 fn7549.1 july 3, 2012 input multiplexer the input of the multiplexer connects the selected analog input pins to the adc input. a proprietary sampling circuit significantly reduces the input drive requiremen ts, resulting in lower overall cost and board space in addition to improved performance. note that the input capacitance is only 2-3pf during the sampling phase, changing to 40pf during the settling phase, resulting in an average input current of 2.5a and an effective input capacitance of only 4pf. see figure 26. voltage reference input an external reference voltage must be supplied to the vref pin to set the full-scale input range of the converter. the vref input on these devices can accept volt ages ranging from 2v (nominal) to vdd, however, they are specified with vref at a voltage of 5v with vdd at 5v. note that exceeding vdd by more than 100mv can forward bias the esd protection diodes and degrade measurement accuracy due to leakage current. a lower value voltage reference must be used if the device is operated with vdd at voltages lower than 5v. if the vref pin is tied to the vdd pin, the vref pin should be decoupled with a local 1f ceramic capacitor as described in a later paragraph. figures 27 and 28 illustrate possi ble voltage reference options for these adcs. figure 27 uses the precision isl21090 voltage reference, which exhibits exceptionally low drift and low noise. the isl21090 must be powered from a supply greater than 4.7v. figure 28 illustrates the isl21010 voltage reference used with these adcs. the isl21010 series voltage references have higher noise and drift than the isl21090 devices, but operate at lower supply voltages. therefore, these devices can readily be used when these sar adcs operate with vdd at voltages less than 5v. the outputs of isl21090 or th e isl21010 devices should be decoupled with a 1f ceramic capacitor. a 1f, 6.3 v, x7r, 0603 (1608 metric) mlcc type capacitor is recommended for its high frequency performance. the trace length from the vref pin to this capacitor and the voltage reference output should be as short as possible. the isl26310 and isl26313 devices (packaged in 8 pin soic packages) derive their voltage reference from the vdd pin. to achieve best performance, the vdd pin of these devices should be bypassed with the 1f ceramic capacitor mentioned above. power-down/standby modes in order to reduce power consumption between conversions, a number of user-selectable modes can be utilized by setting the appropriate bits in the configuration register. auto power-down (pd0 = 0) reduces power consumption by shutting down all portions of the device except the oscillator and digital interface after completion of a conversion. there is a short recovery period after cnv is asserted low (150s with external reference). in auto sleep mode (pd1 = 1), the device will automatically enter the low-power sleep mode at the end of the current conversion. recovery from this mode involves only 2.1s and may offer an alternative to power-down mo de in some applications. output data format the converter output word is delivered in two?s complement format in differential input mode, and straight binary in single-ended input mode of operation respectively, all msb-first. input exceeding the specified full-s cale voltage results in a clipped output which will not return to in-r ange values until after the input signal has returned to the specified allowable voltage range. data must be read prior to the completion of the current conversion to avoid conflict and loss of data, due to overwriting of the new conversion data into the output register. figure 25. relationship between vref and full-scale range for single-ended inputs 3.0 5.0 2.0 1.0 4.0 ain 2.5vpp vref = 2.5v 3.0 5.0 2.0 1.0 4.0 ain 5vpp vref = 5v t v t v figure 26. input sampling operation input voltage offset error ac error total error dc error settling error and noise sampling phase settling phase
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 15 fn7549.1 july 3, 2012 figure 27. precision voltage reference for +5v supply 1 2 3 4 8 7 6 5 dnc vin comp gnd dnc dnc vout trim 0.1f vdd 1f (see text) 2.5v vref 0.1f bulk + 5v isl21090 isl2631x isl2632x figure 28. voltage reference for +2.7v to +3.6v, or for +5v supply vdd 1f (see text) vref 0.1f bulk + +2.7v to +3.6v isl21010 gnd vin vout 1 2 3 0.1f 1.25, 2.048 or 2.5v or +5v isl2631x isl2632x figure 29. voltage reference for isl26310/313 is derived from vdd vdd 1f (see text) bulk +2.7v to +5v isl26310 isl26313 table 1. output codes - differential input voltage two?s complement (12-bit) >(vfs - 1.5 lsb) 7ff vfs - 1.5 lsb 7ff ... 7fe -0.5 lsb 000 ? fff -vfs +0.5 lsb 801 ? 800 note: vfs in the table above equals the voltage between ain+ and ain-. differential full scale is equal to 2* vref. table 2. output codes - single-ended input voltage binary (12-bit) >ain - 1.5 lsb fff ain - 1.5 lsb fff ? ffe 0.5 lsb 001 ? 000 <0.5 lsb 000 note: single-ended full scale is equal to vref.
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 16 fn7549.1 july 3, 2012 serial digital interface the isl26310/11/12/13/14/15/19 family utilizes an spi- compatible interface to set the device configuration and read conversion data. this flexible interface provides 3 modes of operation: reading after conversion (rac), reading during conversion (rdc), and reading spanning conversions (rsc), with an additional option provid ing an end of conversion (eoc) indication on the sdo output in all 3 modes. the choice of operating mode is determined by the timing of the signals on the serial interface. the interface consists of the data clock (sclk), serial digital input (sdi), serial digital output (sdo), and the conversion control input (cnv). from the idle stat e (after completion of a prior conversion), a high-to-low transition on cnv indicates the beginning of input signal acquisit ion, with the conversion then initiated by a subsequent low-to-high transition. when cnv is low, input data presented to sdi is latched on the rising edge of sclk. output data will be presen t at sdo on the falling edge of sclk. sdo is in the high-impedance state whenever cnv is high, and activity on sclk should be av oided during this time to avoid corruption of the conversion proc ess. sclk should be low when cnv is high. during the nth conversion, output data indicates the conversion data and configuration settings for the n-1th conversion, while the current configuration settings apply to the n+1th conversion. in order to minimize errors due to digital noise coupling, there should be no activity on the se rial interface after the specified t data period. data should be read before the conversion is completed to avoid the newer results being overwritten resulting in a permanent loss of data. reading after conversion mode without eoc in this mode, data transfer alwa ys occurs during the acquisition phase, supporting the widest variety of interface data rates. figure 30 depicts a timing wavefo rm in this mode. from idle, the device enters the acquisition phase when cnv is taken low. sdo emerges high from a high-impedan ce state, waiting for an sclk to present the msb of the current output data word. the configuration settings can be updated using sdi and at the same time previous conversion results can be read from sdo. after the communication is completed or the required acquisition time (t acq ) has elapsed ? whichever is later ? cnv transitions high indicating the start of conver sion. cnv must be held high continuously for a minimum of 7.2s (at 125ksps) so that the conversion is completed without enabling eoc. subsequently cnv may be asserted low at any time so that the next acquisition phase can begin. this method is suitable for hosts which operate with lower frequency sclk. note that when using slower spi rates the data transfer time can exceed the minimum acquisition time, which will limit the conversion throughput to less than the maximum specified rate. for example, a 12-bit data transfer takes 12s with a 1mhz spi clock. this adds to the 7.2s conversion time for an effective throughput of 52ksps. reading during conversion mode without eoc from idle, the user initiates the input signal acquisition mode by taking cnv low, and then initiates a conversion after t acq by pulsing cnv high. after the conversion starts, data is exchanged on the serial interface while cnv is held low (as shown in figure 31). cnv must also be asserted high before t data to avoid enabling eoc. this method is id eal for hosts with high sclk communication rates to operate the device at the highest conversion rates. at the end of conversion the device enters the idle state. after the host is certain that the conversion is completed (7.2s after conversion is initiated at 125ksps) a new acquisition can be initiated by pulling cnv low which wi ll initiate the acquisition state. reading spanning conversion mode without eoc in applications desiring slower interface data rates and while still maintaining maximum possible throughput, rsc mode can be used to transfer data during both the acquisition and conversion phases, as shown in figure 32. data exchange begins during the acquisition phase until cnv is asserted high to initiate a conversion and sdo returns to the high-impedance state, interrupting the exchange. after cnv is returned low, sdo will return to the state prior to the cnv pulse in order to avoid data loss. once again data exchange occurs when cnv is low. cnv must be asserted high before t data in order to avoid enabling eoc. at the end of conversion the device enters the idle state. after the host is certain that the conv ersion is completed (7.2s after conversion is initiated at 125ksps) a new acquisition can be initiated by pulling cnv low, which will take the device back to acquisition state from idle state.
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 17 fn7549.1 july 3, 2012 figure 30. timing diagram for reading after conversion mode, without eoc figure 31. timing diagram for reading during conversion mode, without eoc figure 32. timing diagram for reading sp anning conversion mode, without eoc acq. acquisition cnv sclk sdi sdo msb msb-1 d15 d14 . . . . . . d1 lsb d5 d4 adc state idle power-up acquisition conversion idle t acq t sclk t sdo_v t sclkl conversion n+1 configuration n+1 conversion result n-1 t sclkh msb msb-1 d15 d14 . . . . . . lsb configuration n+2 conversion result n conversion idle t sdoz_d t cnv_sclk t sdi_h t sdi_su hi-z state conversion n d5 d4 idle cnv sclk sdi sdo d15 d14 . . . . . . d14 . . . . . . adc state idle power-up acquisition conversion idle acquisition conversion t acq t sclk t cnv_clk t sclkl t data t cnv conversion n conversion n+1 configuration n+1 conversion result n-1 configuration n+2 conversion result n t sclkh msb msb-1 d1 lsb msb msb-1 d1 t sdo_v t sdi_h t sdi_su hi-z state d5 d4 d5 d4 idle idle cnv sclk sdi sdo d15 d14 . . . d4 adc state idle power-up acquisition conversion acquisition conversion t acq t sclk t cnv_sclk t sclkl t data t cnv conversion n conversion n+1 configuration n+1 conversion result n-1 configuration n+2 conversion result n t sclkh d12 msb msb-1 d1 lsb d13 hi-z state msb msb-1 d1 t sdo_v t sdi_h t sdi_su d15 d14 d4 . . . msb-1 msb-2 msb-1 msb-2 . . . note: transition from acquisition to conversion mode may occur a fter any integer number of clock cycles (provided that the mini mum t acq is satisfied). . . . d12 d13
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 18 fn7549.1 july 3, 2012 reading after conversion mode, with eoc in this mode (figure 33), after cnv is asserted low to start input acquisition, a data exchange is executed by sclk during the acquisition period. cnv is asserted high briefly to initiate a conversion, forcing sdo to a high-impedance state. sdo returns high when cnv is asserted low during the entire conversion period. at the end of conversion, the device asserts sdo low to indicate that the conversion is complete. this may be used as an interrupt to start the acquisition phase. it should be noted (as indicated in figure 33) that an addi tional pulse on cnv is required at the end of conversion to take the part back to acquisition from idle state. as discussed in the ?reading after conversion mode without eoc? section, the acquisition time (t acq ) may limit the conversion throughput at slower spi clock rates. reading during conversion mode, with eoc from idle, a falling edge on cn v initiates the acquisition mode, and then a rising edge initiates a conversion. after the conversion is initiated, cnv is asserted low once again. data exchange across sdi and sdo can proceed while cnv is low, again observing the requirements of the t data period in order to minimize the effects of digital noise on sensitive portions of the conversion. in this mode, an additional pulse is required on sclk after the completion of the data exchange, to transition sdo to the high-impedance state. later, sdo is asserted low by the device indicating end of conversion. the device then returns to idle. the falling edge of sdo may be used as an interrupt to start the acquisition phase. see figure 34. reading spanning conversion mode, with eoc after initiating an acquisition by bringing cnv low, the user begins exchanging data as previously mentioned, until cnv is asserted high to initiate a conversion and sdo returns to a high-impedance state, interrupting the exchange. and, after cnv is returned low, sdo will return to the state prior to the cnv pulse in order to avoid losing data interrupted by the conversion pulse. see figure 35. the user should take care to observe the t data period in order to minimize the effects of digital noise on sensitive portions of conversion. after completion of the data exchange, an additional pulse on sclk forces sdo to a high-impedance state. at the end of conversion, the device asserts sdo low indicating the end of conversion. the device then returns to idle, waiting for a pulse on cnv to initiate a new acquisition cycle. accessing the configuration register during data readback the configuration register contains the channel address of the current conversion data. the contents can be accessed during a normal data output sequence by continuing to clock data from sdo if the register readback mode is enabled. both 12-bit output data words and the 16-bit configuration word are output in 28 sclk periods, as shown in figure 36, which demonstrates an example sequence. note that sdo goes into the high-impedance state when cnv is high. the conf iguration register can be read during any read sequence by ge nerating the additional sclks, with the restriction that the sequ ence must be completed prior to the end of the current conversion. this will prevent loss of data due to overwriting of the new conversion data into the output and configuration registers. figure 33. timing diagram for reading after conversion mode with eoc on sdo output acq. acquisition cnv sclk sdi sdo msb msb-1 d15 d14 . . . . . . d1 lsb adc state idle power-up acquisition conversion idle t acq t sclk t sdo_v t sclkl conversion n+1 configuration n+1 conversion result n-1 t sclkh msb msb-1 d15 d14 . . . . . . lsb configuration n+2 conversion result n conversion idle t cnv_sclk t sdi_h t sdi_su hi-z state t cnv conversion n d5 d4 d5 d4
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 19 fn7549.1 july 3, 2012 figure 34. timing diagram for reading during conversion mode with eoc on sdo output figure 35. timing diagram for reading spanning conversions mode with eoc on sdo output figure 36. timing diagram for reading after conv ersion with register readback, without eoc idle idle cnv sclk sdi sdo d15 d14 . . . . . . d14 . . . . . . adc state idle power-up acquisition conversion acquisition conversion t acq t sclk t cnv_clk t sclkl t data t cnv conversion n conversion n+1 configuration n+1 conversion result n-1 configuration n+2 conversion result n t sclkh msb msb-1 d1 lsb msb msb-1 d1 t sdo_v t sdi_h t sdi_su hi-z state d5 d4 d5 d4 idle cnv sclk sdi sdo d15 d4 adc state idle power-up acquisition conversion idle acquisition conversion t acq t sclk t cnv_sclk t sclkl conversion n conversion n+1 configuration n+1 conversion result n-1 configuration n+2 conversion result n t sclkh msb msb-1 d1 lsb hi-z state msb msb-1 d1 t sdo_v t sdi_h t sdi_su d15 d14 d4 . . . msb-1 msb-2 . . . msb-1 msb-2 note: transition from acquisition to conversion mode may occur after any integer number of clock cycles (provided that the mini mum t acq is satisfied). t data t cnv d14 . . . d12 d13 d12 d13 . . . cnv sclk sdi sdo msb msb-1 d15 d14 . . . . . . d1 lsb adc state idle power-up acquisition conversion idle configuration n+1 conversion result n-1 hi-z state conversion n cfg15 cfg14 . . . cfg1 cfg0 configuration settings of n-1 result d5 d4
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 20 fn7549.1 july 3, 2012 device configuration registers the input multiplexer channel select and power management features are controlled by loading the appropriate bits into the 16-bit configuration register thro ugh the serial port, msb-first, as shown below. the first two load bits ld1-ld0 must be set to ?11? in order to perform a register update: any other setting will leave the register unchanged. changes to the configuration register will be implemented internally immediately following the completion of the current conversion, or require a dummy conversion in order to take effect. also, in the case of all power management features, a recovery time will be incurred when returning to normal operation, as indicated. power management modes in all spi interface modes (rac, rdc, etc.) the device has three states of operation: acquisitio n, conversion and idle. power management modes decide the state of the adc in idle mode and are selected by the pm bits in the configuration register as shown in table 3 and table 4. in the default mode (continuous operation) the adc is fully powered in the idle state and can be taken back to the acquisition state instantaneously. in this mode the adc can be operated with maximum throughput and hence is ideally suitable for applications where the ad c is operated continuously. in auto sleep mode the isl263xx will be in a sleep state consuming less than 0.4ma. however, it should be noted that the requirements on t acq are more stringent in auto sleep mode since the device must wake up and then perform the acquisition. in auto power down mode (as selected by pm bits) the adc will be in power-down condition during the idle period, consuming less than 5a of current. wake-up time ta kes 150s. the acquisition time (t acq ) must be increased to account for this delay. the power management modes provide a high degree of flexibility in trading average power consumption versus the required throughput. significant power savings can be achieved by operating in either auto sleep mode or auto power-down mode depending on the throughput requirements. table 3. configuration register bit 15 (msb) 14 13 12 11 10 9 8 ld1 ld0 addr2 addr1 addr0 pm1 pm0 unused bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rgrd unused table 4. configuration register 2 bit(s) description 15:14 register load word, set to ?11? to update registers, otherwise previous settings are retained. 13:11 multiplexer channel select word addr2:0. 000h: channel ain0 (single-ended input devices) or ain0+/ain0- (differential input devices) 001h: channel ain1 or ain1+/ain1- 010h: channel ain2 or ain2+/ain2- 011h: channel ain3 or ain3+/ain3- 100h: channel ain4 101h: channel ain5 110h: channel ain6 111h: channel ain7 10:9 power management configuration control 00h: auto power-down mode. device will go into power-down mode automatically at the end of the next conversion cycle. 01h: continuous operation mode (default). device remains fully powered at all times. 1xh: auto sleep mode. device will enter reduced-power sleep mode automatically at the end of the next conversion cycle. a "1" in pm1 overrides the setting in pm0. 8unused 7 register readback mode. "1" means register readback is enabled resulting in configuration settings to be output along with conversion results. "0" (default) mode of operation register settings are not output. 6:0 unused
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 21 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7549.1 july 3, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl26310 , isl26311 , isl26312 , isl26313 , isl26314 , isl26315 , isl26319 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change june 22, 2012 fn7549.1 added part numbers isl26310, isl26311, isl26313 throughout document added soic package throughout document updated features list by removing following bullets: o 125ksps conversion rate o pin-compatible 2/4-channel differenti al or 4/8-channel single-ended inputs o internal 2.5v reference o available in popular tssop package o pb-free (rohs compliant) updated functional block diagram on page 1 by removing voltage reference updated pin compatible family by removing isl264xx parts updated pin description table to include all parts updated conditions in electrical spec table from: electrical specifications vref+ = vdd(external) v, vdd = 3.3v to 5v, vcm = vdd/2, sclk = 20mhz... to: electrical specifications vref = vdd v, vdd = 2.7v to 5v, vcm = vdd/2, sclk = 20mhz... removed vrefin specs from voltage reference section removed test level from tacq in auto power down mode replaced figures 3 and 4 dnl and inl replaced figure 17 by changing from single line curve to frequency mode rewrote functional description section january 11, 2012 fn7549.0 initial release.
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 22 fn7549.1 july 3, 2012 package outline drawing m16.173 16 lead thin shrink sma ll outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
isl26310, isl26311, isl26312, isl 26313, isl26314, isl26315, isl26319 23 fn7549.1 july 3, 2012 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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